Samsung shows off new roadmap with fabrication down to 3nm

New transistor tech used to go below 4nm

Fabrication down to 3nm

At Samsung Foundry Forum 2018, the semiconductor giant has revealed a series of new process technology improvements targeting high-performance computing and connected devices.

Samsung’s new roadmap focuses on providing its customers with more energy efficient systems for system-on-chip devices targeting a wide variety of industries. “The trend toward a smarter, connected world has the industry demanding more from silicon providers,” says Charlie Bae, executive vice president and head of Foundry Sales & Marketing.

The next process technology to arrive from Samsung is 7nm Low Power Plus based on EUV lithography. Samsung’s 7LPP solution will go into production during the second half of this year and will be scaled up during the first half of 2019.

Moving smaller still, 5nm Low Power Early will be a scaled-down version of 7LPP with improved power consumption figures. After 5nm, Samsung is targeting 4nm Low Power Early and Low Power Plus. At 4nm, this will be the last generation to use FinFET technology. This small step between 5nm and 4nm is designed to allow for easy conversion while still achieving performance improvements.

The last stop on Samsung’s roadmap is 3nm Gate-All-Around Early/Plus. Using the newer type of transistor allows for physical scaling issues with FinFETs to be solved. Samsung is calling their gate-all-around devices MBCFETs, or rather Multi-Bridge-Channel FETs. Each uses a nano-sheet to improve control of the gate.

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